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INTEGRATED CIRCUITS
74ALS161B/74ALS163B 4-bit binary counter
Product specification IC05 Data Handbook 1991 Feb 08
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
FEATURES
74ALS161B/74ALS163B
4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset
DESCRIPTION
Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 - D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 - Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 - Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
* Synchronous counting and loading * Two count enable inputs for n-bit cascading * Positive edge-triggered clock * Asynchronous reset (74ALS161B) * Synchronous reset (74ALS163B) * High speed synchronous expansion * Typical count rate of 140MHz
TYPICAL SUPPLY CURRENT (TOTAL) 10mA 10mA
TYPE 74ALS161B 74ALS163B
TYPICAL fMAX 140MHz 140MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 74ALS161BN, 74ALS163BN 74ALS161BD, 74ALS163BD 74ALS161BDB, 74ALS163BDB DRAWING NUMBER SOT38-4 SOT109-1 SOT338-1
16-pin plastic DIP 16-pin plastic SO 16-pin plastic SSOP Type II
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D3 CEP CET CP PE MR SR Q0 - Q3 TC Data inputs Count enable parallel input (active-Low) Count enable trickle input (active-Low) Clock input (active rising edge) Parallel enable input (active-Low) Asynchronous master reset input (active-Low) for 74ALS161B Asynchronous reset input (active-Low) for 74ALS163B Flip-flop outputs Terminal count output (active-Low) DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 20/80 20/80 LOAD VALUE HIGH/LOW 20A/0.1mA 20A/0.1mA 20A/0.1mA 20A/0.1mA 20A/0.1mA 20A/0.1mA 20A/0.1mA 0.4mA/8mA 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20A in the High state and 0.1mA in the Low state.
1991 Feb 08
2
853-1350 01670
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
SF00664
APPLICATIONS
VCC
PE CEP CET CLOCK CP SR
D0 D1
D2 D3
74ALS163B
TC
Q0 Q1 Q2 Q3
SC00086
Figure 1. Maximum Count Modifying Scheme Terminal Count = 6
H H = Enable count or L L = Disable count
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
D0 D1 D2 D3 PE CEP 74ALS163B CET TC CP SR Q0 Q1 Q2 Q3
CP
SC00087
Figure 2. Synchronous Multistage Counting Scheme
1991 Feb 08
3
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
PIN CONFIGURATION - 74ALS161B
MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
PIN CONFIGURATION - 74ALS163B
SR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
SF00656
SF00657
LOGIC SYMBOL - 74ALS161B
3 4 5 6
LOGIC SYMBOL - 74ALS163B
3 4 5 6
9 7 10 2 1
PE CEP CET CP MR
D0
D1
D2
D3
9 7 TC 15 10 2
PE CEP CET CP SR
D0
D1
D2
D3
TC
15
Q0
Q1
Q2
Q3
1
Q0
Q1
Q2
Q3
VCC = Pin 16 GND = Pin 8
14
13
12
11
VCC = Pin 16 GND = Pin 8
14
13
12
11
SF00658
SF00659
IEC/IEEE SYMBOL - 74ALS161B
1 9 7 10 2 R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
IEC/IEEE SYMBOL - 74ALS163B
1 9 7 10 2 2R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
3 4 5 6
1,2 D
14 13 12 11 15
3 4 5 6
1,2 D
14 13 12 11 15
4 CT=15
4 CT=15
SF00660
SF00661
1991 Feb 08
4
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
LOGIC DIAGRAM - 74ALS161B
CP MR 2 1
PE CET CEP D0
9 10 7 3 DRQ
CP
Q
14
Q0
D1
4 DRQ
CP
Q
13
Q1
D2
5 DRQ
CP
Q
12
Q2
D3
6 DRQ
CP
Q
11
Q3
15 VCC = Pin 16 GND = Pin 8
TC
SF00662
MODE SELECTION FUNCTION TABLE - 74ALS161B
INPUTS MR L H H H h h H= h= L= l= qn = X= (a) = = CP X X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X L L H count qn qn OUTPUTS Qn TC L L (a) (a) (a) L Reset (clear) Parallel load Count Hold (do nothing) OPERATING MODE
High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don't care The output is High when CET is High and the counter is at terminal count (HHHH) Low-to-High clock transition
1991 Feb 08
5
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
LOGIC DIAGRAM - 74ALS163B
CP SR 2 1
PE CET CEP D0
9 10 7 3 D Q
CP
Q
14
Q0
D1
4 D Q
CP
Q
13
Q1
D2
5 D Q
CP
Q
12
Q2
D3
6 D Q
CP
Q
11
Q3
15
TC
VCC = Pin 16 GND = Pin 8
SF00663
MODE SELECTION FUNCTION TABLE - 74ALS163B
INPUTS SR l h h h h h H= h= L= l= qn = X= (a) = = CP X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X L L H count qn qn OUTPUTS Qn TC L L (a) (a) (a) L Reset (clear) Parallel load Count Hold (do nothing) OPERATING MODE
High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don't care The output is High when CET is High and the counter is at terminal count (HHHH) Low-to-High clock transition
1991 Feb 08
6
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 16 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -0.4 8 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VO OH VO OL VIK II IIH IIL IO ICC PARAMETER High-level High level output voltage Low-level Low level output voltage Input clamp voltage Input current at minimum input voltage High-level input current Low-level input current Output current3 Supply current (total) TEST CONDITIONS1 VCC = 10%, VIL = MAX, , , VIH = MIN VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.4V VCC = MAX, VO = 2.25V VCC = MAX -30 10 IO = -0.4mA 0 4mA OH IOL = 4mA IOL = 8mA LIMITS MIN VCC - 2 0.25 0.35 -0.73 0.40 0.50 -1.5 0.1 20 -0.1 -112 21 TYP2 MAX UNIT V V V V mA A mA mA mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
1991 Feb 08
7
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum clock frequency Propagation delay CP to Qn Propagation delay CP to TC Propagation delay CET to TC Propagation delay MR to Qn Propagation delay MR to TC 74ALS161B 74ALS163B Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 3 Waveform 3 100 4.0 6.0 6.0 8.0 3.0 3.0 8.0 11.0 13.0 16.0 16.0 16.0 10.0 10.0 15.0 19.0 MAX MHz ns ns ns ns ns UNIT
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(L) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low PE or SR to CP Hold time, High or Low PE or SR to CP Setup time, High or Low CET or CEP to CP Hold time, High or Low CET or CEP to CP CP Pulse width (load), High or Low CP Pulse width (count), High or Low MR or SR Pulse width, Low Recovery time, CR or SR to CP Waveform 6 Waveform 6 Waveform 5 or 6 Waveform 6 Waveform 4 Waveform 4 Waveform 1 Waveform 1 Waveform 3 Waveform 3 8.0 8.0 0.0 0.0 10.0 10.0 0.0 0.0 10.0 10.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 10.0 MAX ns ns ns ns ns ns ns ns ns ns UNIT
1991 Feb 08
8
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
AC WAVEFORMS
For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
CP
VM tw(H) tPLH
VM tw(L)
VM tPHL
CET
VM tPLH
VM tPHL
Qn, TC
VM
VM
TC
VM
VM
SC00088
SF00668
Waveform 1. Propagation Delay for Clock Input to Output, Clock PUlse Width, and Maximum Clock Frequency
Waveform 2. Propagation Delay for CET to TC Output
tw(L) MR VM VM CEP tREC CET VM tPHL CP VM tsu(H) VM th(H) VM tsu(L) VM th(L)
CP
VM
VM
Qn, TC
VM
SF00669
SC00089
Waveform 3. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time
Waveform 4. CEP and CET Setup and Hold Times
Dn
VM tsu
VM th
SR
VM tsu(L)
VM th(L)
VM tsu(H)
VM th(H)
PE
VM tsu(L)
VM th(L)
VM tsu(H)
VM th(H)
CP
VM
VM
CP
VM
VM
SC00090
SC00091
Waveform 5. Synchronous Reset Setup and Hold Times
Waveform 6. Data and Parallel Enable Setup and Hold Times
1991 Feb 08
9
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B/74ALS163B
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tff) CL RL tw VM 10% tTLH (tr ) 0.3V 90% AMP (V)
tTLH (tr ) 90%
tTHL (tf ) AMP (V) 90% VM tw 10% 0.3V
Test Circuit for Totem-pole Outputs
POSITIVE PULSE 10%
VM
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate 1MHz tw 500ns tTLH 2.0ns tTHL 2.0ns
SC00005
1991 Feb 08
10
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
SOT38-4
DIP16: plastic dual in-line package; 16 leads (300 mil)
1991 Feb 08
11
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
SOT109-1
SO16: plastic small outline package; 16 leads; body width 3.9 mm
1991 Feb 08
12
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
SOT338-1
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
1991 Feb 08
13
Philips Semiconductors
Product specification
4-bit binary counter
74ALS161B 74ALS163B
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1991 Feb 08 14

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